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2023年第一届研究、创新、创意展
(R.I.C.E'23)
Project ID:
SCEN107
Design 32-bits RISC Processor using Verilog HDL
Project Title:
Category:
Science & Engineering
Inventors:
Teoh Jess Yin
Institution/Company:
Southern University College
Invention Description/ Abstract:
RISC(Reduced Instruction Set Computer) is an architecture of the current CPU. Like ARM, as a kind of RISC, has important functions in smart phones, wearable devices and other mobile processors.
RISC architecture requires the specification of each operation step, which can reduce the complexity of CPU and allow to produce more powerful CPU with the same technology level, but it has higher requirements for the design of compiler.
Invention Technical Description
Design the functional units of the RISC processor, and implement them with Verilog HDL using software Quartus Prime.
Demostration/ Presentation Video
Poster/ Broucher/ Invention Photo
Video Link
Poster Link
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